1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to circuit power reduction using micro-electromechanical (MEM) switches.
2. Related Art
As integrated circuit ground rules and manufacturing techniques allow for smaller and smaller device sizes, the power consumption of these circuits climbs rapidly. As a result of shorter transistor channel lengths, thinner gate oxide, and increased numbers of transistors, leakage current is quickly becoming a dominant power consumer in today's integrated circuit designs.
An example of increased power consumption is associated with the use of latches in integrated circuits to improve testability, test coverage, observability, and overall logical data flow control. These types of latches, which are not always used in the functional operation of an integrated circuit, add loading to the functional circuitry of the integrated circuit and also consume power due to high leakage currents and/or power dissipation during operation.
Traditional storage latches, such as a Data latch (“D-latch”), are implemented using various circuit layouts. One such D-latch layout 10 is illustrated in FIG. 1. When the clock input (“CLK”) to the D-latch 10 is logic 1, the Q output will always reflect the logic level present at the D-latch input D. When the CLK input falls to logic 0, the last state of the D-latch input D is trapped, or latched, for use by whatever other circuits may be using this signal. Many other types of storage latch designs are well known in the art.
Traditional storage latch designs may be implemented in any common semiconductor chip fabrication process such as Complementary Metal Oxide Semiconductor (CMOS), bipolar, bipolar CMOS (BiCMOS), silicon germanium (SiGe), etc. Today's design techniques implement these latch designs using standard transistor-based methods that insure compatibility with today's design techniques. Unfortunately, current latch designs have significant drawbacks: power dissipation when active and leakage currents are not in use, thus driving integrated circuit power requirements higher. Each latch used in an integrated circuit adds to the total dynamic and static power consumption of the integrated circuit. This power consumption becomes non-trivial as transistor sizes continue to decrease, device speeds increase and the number of latches used by integrated circuits increases.
Accordingly, there is a need for a circuit design that isolates logic blocks (e.g., latches) when they are non-operational, thus reducing power consumption and improving performance, while minimally impacting overall size of the design.